Sassine Ghazi
President and Chief Executive Officer at Synopsys
Good afternoon. We had a solid start to 2025, exceeding the midpoint of our Q1 revenue guidance and delivering non-GAAP EPS above our guidance range. As we outlined in December, Q1 revenue was down 4% year-over-year, and non-GAAP EPS was down 10% as we had one less work week in Q1 '25 versus Q1 '24.
Let me take a few minutes to share some business highlights, and then Sheila will discuss the financials in more detail. From an end market perspective, AI and HPC remained robust in the first quarter, while industrial, automotive and consumer electronics remained challenged. Despite the sale of two markets, along with headwinds in China as we anticipated, Synopsys opportunity is tied to R&D and underpinned by the mega trends of AI and silicon proliferation and software-defined systems. These trends are increasing design complexity and cost while driving greater compute and energy demands.
New design paradigms are essential to address these challenges and Synopsys is racing to deliver. I had the privilege to meet with semi and automotive customers at in January, who all expressed their strong belief in the strategy we are driving. They underscored the pressing need for solutions to design, validate and optimize intelligent products virtually from silicon to systems.
Our pending acquisition of ANSYS will pave the way for new AI-powered design solutions that use electronics and physics giving R&D teams the tools they need to ignite their future innovation. In January, the European Commission approved our pending procompetitive acquisition of ANSYS and the U.K. CMA provisionally accepted our remedies toward the Phase 1 approval.
As previously communicated, the U.S. HSR Act waiting period has expired. And we're making strong progress with other regulatory agencies, including China. Customers overwhelmingly support this transaction and we continue to anticipate closing in the first half of 2025.
Moving to business highlights. In Q1, Design Automation revenue was up 4% year-over-year with 1 less week of revenue versus the prior Q1, while design activity remained strong. Synopsys is the leader in hardware-assisted verification or HAV solutions. And this month, we strengthened our position expanding our industry-leading HAV portfolio to include new HAPS 200 prototyping systems and new ZeBu 200 emulation systems with up to 2x better performance versus our prior generation. AMD, ARM, NVIDIA and are among a number of customers who are deploying our new prototyping and emulation technologies, and we were honored by their participation in our recent launch.
Last year, we had our best year ever in hardware, and we expect another year of strong performance based on the enthusiasm for our newly expanded Synopsys HAV portfolio. which provides the unmatched performance and flexibility our customers require to prototype emulate and verify ever more integrated complex and software-defined systems.
Turning to EDA software, where we are seeing strong design activity at advanced nodes with 2-nanometer projects accelerating rapidly. Fusion Compiler is the industry-leading platform for advanced node digital design implementation. And this quarter, we saw a U.S. hyperscaler tape out a 2-nanometer test chip exclusively using Synopsys design flow. Additionally, at 2-nanometer, Fusion Compiler was the platform of choice for a U.S. HPC, CPU tape-out and an Asian mobile customers 2-nanometer at SOC.
Moving to Synopsys technologies where we offer the industries essential trusted solutions to close out timing, signal integrity, power and variation aware analysis. Headlining our portfolio is prime time. which is used by virtually all key advanced node customers. Customers are reporting significant productivity improvements with the most recent prime time release with one customer achieving 30% faster turnaround time with multi-core scaling.
Our IC Validator product family is delivering tremendous value and physical verification sign-off. And recent product improvements have unleashed even greater turnaround time improvements for customers. Leading edge customers are achieving greater than 2x turnaround time for full chip physical verification sign-off at 3-nanometer and below, enabling design teams to finish more sign-off runs within the budget cycle time to improve the quality of results.
Before moving out of sign-off, a few points on Star RC, which is the industry-leading tool for extraction on advanced process nodes. To date, we've seen all of our major CPU and GPU customers on TSMC and Intel 18A using STAR RC for sign-off extraction with the key differentiation being the accuracy of results and tool performance relative to competition. The massive AI infrastructure build-out that's currently underway paves the way for a transformation across all industries, including our own. AI is fueling chip innovation and the AI-driven EDA capabilities we pioneered from reinforcement learning to generative AI capabilities are delivering significant productivity gains and cementing our leadership position, but we're only at the beginning.
While customers are realizing compelling value from our initial AI-driven optimization engines, these enhanced capabilities have not yet dramatically altered the underlying design flow for a chip. We see a paradigm shift coming with agent AI where engineers can task autonomous agents with executing complex workflows. We believe this will be massive value and productivity unlock for our industry. Which we'll talk more about at our Synopsys User Group Conference in March. But first, AI business highlights from this quarter.
In Q1, we continue to drive Synopis.ai adoption across our tools in design implementation, verification, test and analog. In verification or VSO.ai, we saw a large U.S. memory company begin deployment of VSO.ai to find corner case bugs realize a 2x improvement in hardware utilization, while an Asian hyperscale customer achieved a 4x turnaround time improvement with VSO.ai on its HPC design, significantly improving hardware utilization and outperforming the competition.
Our analog migration tool, ASO.ai continues to build a strong pipeline of customer opportunities and in Q1 delivered a significant competitive displacement at a leading aerospace company. We also continue to expand our generative AI offerings for customers. We recently added script generation capabilities to the core pilots for Fusion Compiler and prime time, and early customer results are demonstrating 30% average productivity improvements for designers.
Additionally, synopsys.ai generative formal verification capability in Verde is delivering up to a 35% productivity boost in early engagements with key partners. On to design IP, in line with our expectations, revenue was down 17% year-over-year versus a record setting prior year compare. While IP revenue can fluctuate quarter-to-quarter, the opportunity set for IP continues to expand, particularly as AI customers accelerate protocol transitions and look for creative ways to drive enhanced performance per watt.
This quarter, we launched the industry's first Ultra Accelerator Link, or UAL and Ultra Ethernet IP solutions to connect massive AI accelerator clusters addressing the industry need for open standard solutions to scale AI accelerator infrastructure. We also continue to optimize our foundation IP libraries to deliver unparalleled AI performance. One, high-performance AI customer used our memory and logic libraries to deliver breakthrough LLM performance at 5-nanometer. Across our interface IP portfolio, AI continues to push protocols forward at breakneck pace as customers drive for additional performance per watt.
This quarter, we captured several key design wins, including aKind Edge PCIe 7.0 design with an AI infrastructure chip provider, and we secured a 224 gig ethernet win with a major ecosystem player. We also secured 112-gig SerDes and PCIe 6.0 agreement with a leading European telecommunications equipment provider and an interface IP development deal for a leading auto OEMs advanced 2-nanometer design.
Our IP development for the foundry ecosystem is a mission-critical ingredient for the industry. And in Q1, we announced silicon success for PCIe 4.05 IP on Samsung's SS-8 process used in auto, mobile, networking and storage applications. Also in Q1, we demonstrated silicon success for our onetime programmable nonvolatile memory IP. This technology enables secure storage for encryption keys, product configuration and SRAM repair information and is now available in TSMC N4 and N5 and N6 and N7 processes.
Moving to mobile and consumer markets, where end market demand is challenging, but design activity continues as customers ready a next wave of innovative products. A leading Asian automotive supplier adopted Synopsys interface processor and foundation IP due to our long track record of delivering high-quality IP. Also in Q1, we closed the design win, including PCIe 4.0 MIPI and USB with a leading mobile provider for an ARM-based application processor. UFS or universal flash storage is a key technology in these verticals. And we closed a UFS design with a key company driving a AIPCs this quarter.
We also continue to see strong demand for the advanced UFS protocol in mobile to support LLM storage for Gen AI use cases. A few closing comments before we transition to Shelagh's remarks, we have a very resilient business model, and our solutions are mission-critical to our customers' innovation. We have strong momentum across the business, bolstered by secular growth tailwinds, including AI. The application of AI for EDA and engineering more broadly is just beginning, which we'll discuss in more detail at Snug in March.
Finally, thank you to our employees, customers and partners for a strong start to 2025. We are excited to continue our partnership journey with you through the year. With that, I'll turn it over to Shelagh.